Memory with level shifting word line driver and method thereof
US7440354B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 15, 2006 |
| Grant date | Oct 21, 2008 |
| Priority date | — |
| Expiry date | May 15, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C8/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory includes a bit cell array including a plurality of word lines and address decode circuitry having an output to provide a predecode value. The address decode circuitry includes a first plurality of transistors having a first gate oxide thickness. The memory further includes word line driver circuitry having an input coupled to the output of the address decode circuitry and a plurality of outputs, each output coupled to a corresponding word line of the plurality of word lines. The word line driver includes a second plurality of transistors having a second gate oxide thickness greater than the first gate oxide thickness. A method of operating the memory also is provided.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.