Method of manufacturing a transistor and a method of forming a memory device with isolation trenches

US7442609B2 · kind B2 · utility

Assignee

• Infineon Technologies AG · DE

Inventors

• Peng Wang · Longbeilingcun, CN
• Joachim Nuetzel · Fishkill, US
• Rolf Weis · Dresden, DE
• Till Schloesser · Dresden, DE
• Marc Strasser · Munich, DE
• Richard Luyken · Munich, DE

Key dates

• Filing date: Sep 9, 2005
• Grant date: Oct 28, 2008
• Expiry date: Nov 10, 2026

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D89/10
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

A method of manufacturing a transistor. In one embodiment, the method includes forming a gate electrode by defining a gate groove in the substrate. A plate-like portion is defined in each of the trenches at a position adjacent to the groove so that the two plate-like portions will be connected with the groove and the groove is disposed between two plate-like portions. In one embodiment, the two plate-like portions are defined by an etching process which selectively etches the isolating material of the isolation trenches with respect to the semiconductor substrate material. A gate insulating material is provided at an interface between the active area and the groove and the interface between the active area and the plate-like portions, and a gate electrode material is deposited so as to fill the groove and the two plate-like portions.