Method to engineer etch profiles in Si substrate for advanced semiconductor devices
US7442618B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Jul 16, 2005 |
| Grant date | Oct 28, 2008 |
| Priority date | — |
| Expiry date | Aug 3, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/822
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Structures and methods for forming keyhole shaped regions for isolation and/or stressing the substrate are shown. In a first embodiment, we form an inverted keyhole shaped trench in the substrate in the first opening preferably using a two step etch. Next, we fill the inverted keyhole trench with a material that insulates and/or creates stress on the sidewalls of the inverted keyhole trench. In a second embodiment, we form a keyhole stressor region adjacent to the gate and isolation structures. The keyhole stressor region creates stress near the channel region of the FET to improve FET performance. The stressor region can be filled with an insulator or a semiconductor material.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.