Generation of memory test patterns for DLL calibration
US7444559B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 28, 2004 |
| Grant date | Oct 28, 2008 |
| Priority date | — |
| Expiry date | Jun 18, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/318328
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A system and method to generate memory test patterns for the calibration of a delay locked loop (DLL) using pseudo random bit sequences (PRBS) generated through a pair of liner feedback shift registers (LFSR). The generated patterns are implemented on the system data bus as test patterns that closely simulate run-time switching conditions on the system bus, so as to allow more accurate calibration of the DLL. Test data write/read operations may be performed while signals for the test patterns are present on various bit lines in the data bus so as to allow for accurate determination or adjustment of the value for the delay to be provided by the DLL to the strobe signals during memory data reading operations at run time. Memory chips may also be tested over an operating range of values using the generated test patterns.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.