Architecture and method for testing of an integrated circuit device
US7444575B2 · kind B2 · utility
27Cited by
94References
54Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Aug 19, 2005 |
| Grant date | Oct 28, 2008 |
| Priority date | — |
| Expiry date | Jan 15, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/31917
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
In one embodiment, the present invention provides a platform of hardware and/or software that enables the complete access and reliable testing of multiple integrated circuit (IC) devices within a package. This platform may include a testing component (e.g., test circuits, test pads, shared pads, etc.), one or more probe cards and related hardware, wafer probe programs, load board and related hardware of external test equipment, and software and routines for final test programs.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.