Method and system for evaluating timing in an integrated circuit

US7444608B2 · kind B2 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Eric A. Foreman · Saint Albans, US
• Peter A. Habitz · South Burlington, US
• David J. Hathaway · Underhill Center, US
• Jerry D. Hayes · Georgetown, US
• Anthony D. Polson · Jericho, US

Key dates

• Filing date: May 15, 2006
• Grant date: Oct 28, 2008
• Expiry date: Dec 20, 2026

Classification

• Technology area (CPC G): Physics
• CPC primary: G01R31/3016
• WIPO field: Measurement
• WIPO sector: Instruments

Abstract

Methods for analyzing the timing in integrated circuits and for reducing the pessimism in timing slack calculations in static timing analysis (STA). The methods involve grouping and canceling the delay contributions of elements having similar delays in early and late circuit paths. An adjusted timing slack is calculated using the delay contributions of elements having dissimilar delays. In some embodiments, the delay contributions of elements having dissimilar delays are root sum squared. Embodiments of the invention provide methods for reducing the pessimism due to both cell-based and wire-dependent delays. The delays considered in embodiments of the invention may include delays due to the location of elements in a path.