Inventor · Jericho, VT, US

Anthony D. Polson

27Patents

7h-index

28Co-inventors

61Inventor score

Filing activity: Apr 29, 2004 → Sep 25, 2012

Most-cited inventions

Patent	Title	Area	Cited by	Status
US7089143B2	Method and system for evaluating timing in an integrated circuit	Physics	25	Expired
US7401307B2	Slack sensitivity to parameter variation based timing analysis	Physics	17	Expired
US7810054B2	Method of optimizing power usage of an integrated circuit design by tuning selective voltage binning cut point	Physics	10	Active
US7489204B2	Method and structure for chip-level testing of wire delay independent of silicon delay	Physics	9	Active
US7877714B2	System and method to optimize semiconductor power by integration of physical design timing and product performance measurements	Physics	9	Active
US7280939B2	System and method of analyzing timing effects of spatial distribution in circuits	Physics	8	Expired
US7716616B2	Slack sensitivity to parameter variation based timing analysis	Physics	8	Active
US7444608B2	Method and system for evaluating timing in an integrated circuit	Physics	7	Active
US7418689B2	Method of generating wiring routes with matching delay in the presence of process variation	Physics	7	Active
US7890906B2	Method of laying out integrated circuit design based on known polysilicon perimeter densities of individual cells	Physics	6	Active
US7487487B1	Design structure for monitoring cross chip delay variation on a semiconductor device	Physics	5	Active
US9310426B2	On-going reliability monitoring of integrated circuit chips in the field	Physics	5	Active
US7840864B2	Functional frequency testing of integrated circuits	Electricity	5	Active
US9075106B2	Detecting chip alterations with light emission	Physics	4	Active
US7849433B2	Integrated circuit with uniform polysilicon perimeter density, method and design structure	Physics	4	Active
US7765351B2	High bandwidth low-latency semaphore mapped protocol (SMP) for multi-core systems on chips	Physics	3	Active
US7870525B2	Slack sensitivity to parameter variation based timing analysis	Physics	3	Active
US7302673B2	Method and system for performing shapes correction of a multi-cell reticle photomask design	Physics	3	Expired
US7962874B2	Method and system for evaluating timing in an integrated circuit	Physics	3	Active
US7865861B2	Method of generating wiring routes with matching delay in the presence of process variation	Physics	3	Active
US7290191B2	Functional frequency testing of integrated circuits	Electricity	3	Expired
US7840863B2	Functional frequency testing of integrated circuits	Electricity	2	Active
US7823115B2	Method of generating wiring routes with matching delay in the presence of process variation	Physics	2	Active
US7805693B2	IC chip design modeling using perimeter density to electrical characteristic correlation	Physics	2	Active
US7521973B1	Clock-skew tuning apparatus and method	Electricity	2	Active

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.