Process for manufacturing an integrated circuit system
US7444735B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 2, 2005 |
| Grant date | Nov 4, 2008 |
| Priority date | — |
| Expiry date | Aug 3, 2026 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T29/49155
- WIPO fieldControl
- WIPO sectorInstruments
Abstract
A system for manufacturing an integrated circuit system having a substrate with a integrated circuit device. A first pad is formed on the substrate and connected to the integrated circuit device. A first dielectric layer is formed over the substrate and the first pad, with the first dielectric layer having an opening provided therein exposing the first pad. An upper redistribution layer is formed over the first dielectric layer. A portion of the upper redistribution layer is formed into an antenna with the antenna connected to the first pad. A second dielectric layer is formed over the first dielectric layer and over the antenna.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.