Method for forming a dual metal gate structure

US7445981B1 · kind B1 · utility

Assignee

• Freeescale Semiconductor, Inc. · US

Inventors

• Gauri Karve · Cohoes, US
• Cristiano Capasso · Austin, US
• Srikanth B. Samavedam · Austin, US
• James K. Schaeffer · Austin, US
• William J. Taylor, Jr. · Clifton Park, US

Key dates

• Filing date: Jun 29, 2007
• Grant date: Nov 4, 2008
• Expiry date: Jul 12, 2027

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/0181

Abstract

A method includes forming a first gate dielectric layer over a semiconductor layer having a first and a second well region, forming a first metal gate electrode layer over the first gate dielectric, forming a sidewall protection layer over the first metal gate electrode layer and adjacent sidewalls of the first gate dielectric layer and first metal gate electrode layer, forming a channel region layer over the second well region, forming a second gate dielectric layer over the channel region layer, forming a second metal gate electrode layer, and forming a first gate stack including a portion of each of the first gate dielectric layer and first metal gate electrode layer over the first well region and forming a second gate stack including a portion of each of the second gate dielectric layer and second metal gate electrode layer over the channel region layer and over the second well region.