Inventor · Cohoes, NY, US

Gauri Karve

78Patents

6h-index

81Co-inventors

71Inventor score

Filing activity: May 1, 2007 → Nov 15, 2022

Most-cited inventions

Patent	Title	Area	Cited by	Status
US9721848B1	Cutting fins and gates in CMOS devices	Electricity	17	Active
US9287264B1	Epitaxially grown silicon germanium channel FinFET with silicon underlayer	Electricity	11	Active
US8017469B2	Dual high-k oxides with sige channel	Electricity	10	Active
US8460996B2	Semiconductor devices with different dielectric thicknesses	Electricity	7	Active
US7445981B1	Method for forming a dual metal gate structure	Electricity	7	Active
US9331148B1	FinFET device with channel strain	Electricity	6	Active
US7709331B2	Dual gate oxide device integration	Electricity	5	Active
US7749829B2	Step height reduction between SOI and EPI for DSO and BOS integration	Electricity	5	Active
US10381437B2	Semiconductor device and method of forming the semiconductor device	Electricity	4	Active
US10734523B2	Nanosheet substrate to source/drain isolation	Performing Operations; Transporting	4	Active
US9881937B2	Preventing strained fin relaxation	Electricity	4	Active
US7666730B2	Method for forming a dual metal gate structure	Electricity	4	Active
US9496371B1	Channel protection during fin fabrication	Electricity	4	Active
US9917196B1	Semiconductor device and method of forming the semiconductor device	Electricity	4	Active
US9431514B2	FinFET device having a high germanium content fin structure and method of making same	Electricity	3	Active
US10833190B2	Super long channel device within VFET architecture	Electricity	3	Active
USRE45955E1	Dual high-K oxides with SiGe channel	General	3	Active
US9576979B2	Preventing strained fin relaxation by sealing fin ends	Electricity	3	Active
US9640640B1	FinFET device with channel strain	Electricity	3	Active
US7790528B2	Dual substrate orientation or bulk on SOI integrations using oxidation for silicon epitaxy spacer formation	Electricity	2	Active
US10062714B2	FinFET device having a high germanium content fin structure and method of making same	Electricity	2	Active
US9711507B1	Separate N and P fin etching for reduced CMOS device leakage	Electricity	2	Active
US9741856B2	Stress retention in fins of fin field-effect transistors	Electricity	2	Active
US9997369B2	Margin for fin cut using self-aligned triple patterning	Electricity	2	Active
US9502411B1	Strained finFET device fabrication	Electricity	2	Active

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.