Low resistance peripheral contacts while maintaining DRAM array integrity
US7445996B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Mar 8, 2005 |
| Grant date | Nov 4, 2008 |
| Priority date | — |
| Expiry date | Aug 31, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/485
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A process and apparatus directed to forming low resistance contacts in both the memory cell array and peripheral logic circuitry areas of a semiconductor device, for example, a DRAM memory device, is disclosed. In a buried bit line connection process flow, the present invention utilizes chemical vapor deposition of titanium to form titanium silicide in contact structures of the peripheral logic circuitry areas and physical vapor deposition to provide a metal mode (metallic) titanium layer in contact with the poly plugs in the memory cell array area of a semiconductor device, for example, a DRAM memory device according to the present invention. In this manner, the present invention avoids the potential drawbacks such as voiding in the poly plugs of the memory cell array due to the present of titanium silicide, which can cause significant reduction of device drain current and in extreme cases cause electrical discontinuity.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.