Stacked integrated circuit leadframe package system
US7446396B2 · kind B2 · utility
2Cited by
10References
10Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jan 11, 2006 |
| Grant date | Nov 4, 2008 |
| Priority date | — |
| Expiry date | Aug 15, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/19107
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A stacked integrated circuit leadframe package system including forming a leadframe, packaging a top integrated circuit on a one side of the leadframe, packaging a bottom integrated circuit on an opposite side of the leadframe, and forming external electrical interconnects on the leadframe.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.