Three-dimensional package and method of making the same

US7446404B2 · kind B2 · utility

Assignee

• ADVANCED SEMICONDUCTOR ENGINEERING, INC. · TW

Inventors

• Min-Lung Huang
• Wei-Chung Wang · Tangxia, CN
• Po-Jen Cheng · Rancho Santa Fe, US
• Kuo-Chung Yee · Taipei, TW
• Ching-Huei Su
• Jian-Wen Lo
• Chian-Chi Lin · Tainan, TW

Key dates

• Filing date: Dec 26, 2006
• Grant date: Nov 4, 2008
• Expiry date: Feb 12, 2027

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L2924/01078
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

A three-dimensional package including a first wafer having at least one first pad and a first protection layer exposing the first pad. A first hole penetrates the first wafer. A first isolation layer is disposed on the side wall of the first hole. The lower end of a first conductive layer extends below the surface of the first wafer. A first metal is disposed in the first hole, and is electrically connected to the first pad via the first conductive layer. A first solder is disposed on the first metal in the first hole, wherein the melting point of the first solder is lower than that of the first metal. A second wafer is configured similarly as the first wafer. A lower end of a second conductive layer of the second wafer extends below the surface of the second wafer and contacts the upper end of the first solder.