Method for operating single-poly non-volatile memory device
US7447082B2 · kind B2 · utility
3Cited by
8References
8Claims
0Family size
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Key dates
| Filing date | Nov 1, 2006 |
| Grant date | Nov 4, 2008 |
| Priority date | — |
| Expiry date | Nov 4, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/021
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A single-poly non-volatile memory cell that is fully compatible with nano-scale semiconductor manufacturing process is provided. The single-poly non-volatile memory cell includes an ion well, a gate formed on the ion well, a gate dielectric layer between the gate and the ion well, a dielectric stack layer on sidewalls of the gate, a source doping region and a drain doping region. The dielectric stack layer includes a first oxide layer deposited on the sidewalls of the gate and extends to the ion well, and a silicon nitride layer formed on the first oxide layer. The silicon nitride layer functions as a charge-trapping layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.