Memory device trims
US7447847B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 19, 2004 |
| Grant date | Nov 4, 2008 |
| Priority date | — |
| Expiry date | Feb 7, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/04
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods and apparatus are provided. A memory device has a memory array, base trim circuitry adapted to store base control parameter values common to the memory array, and a reference trim circuit corresponding to a portion of the memory array. The reference trim circuit is adapted to store one or more reference control parameter values for respectively correcting one or more of the base control parameter values of the base trim circuitry for application to the portion of the memory array. The memory device may include an index circuit corresponding to the reference trim circuit. The index circuit is adapted to store one or more index parameter values for respectively selecting the one or more base control parameter values of the base trim circuitry for correction by the one or more reference control parameter values of the reference trim circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.