Lithography pattern shrink process and articles
US7449230B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 23, 2005 |
| Grant date | Nov 11, 2008 |
| Priority date | — |
| Expiry date | May 25, 2026 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T428/24562
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Novel processes of applying a thin, uniform, conformal organic polymeric film by a wide variety of deposition processes into lithography pattern substrates are provided. The inventive processes result in shrinking of the gaps in the lithography pattern equally, thus producing a smaller dimension. The amount of pattern shrinkage is selectively controlled by controlling the deposition rate to provide the desired final structure dimension. A wide variety of organic films is used as materials for these films. The inventive methods are applicable to any patterning technique used in lithography to provide a reduction in pattern sizes. Examples of the applicable device levels include the production of gate layers, ion implantation of active device layers and substantive metal layers, dielectric patterning, interconnect processes produced by damascene, dual damascene, backend packaging layers, and devices requiring multiple layers deposited by electrodeposition, CVD or sputtering. The inventive methods are useful for providing highly conformal coatings on large surface substrates having super submicron (i.e., 0.15 μm or smaller) features. The process is environmentally friendly and relativ…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.