Trench-gated FET for power device with active gate trenches and gate runner trench utilizing one-mask etch
US7449354B2 · kind B2 · utility
80Cited by
11References
39Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 5, 2006 |
| Grant date | Nov 11, 2008 |
| Priority date | — |
| Expiry date | Apr 27, 2027 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/95
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A trench-gated field effect transistor (FET) is formed as follows. Using one mask, a plurality of active gate trenches and at least one gate runner trench are defined and simultaneously formed in a silicon region such that (i) the at least one gate runner trench has a width greater than a width of each of the plurality of active gate trenches, and (ii) the plurality of active gate trenches are contiguous with the at least one gate runner trench.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.