Memory device and fabrication method thereof
US7449382B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 24, 2006 |
| Grant date | Nov 11, 2008 |
| Priority date | — |
| Expiry date | Jun 30, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/10
Abstract
A memory device is disclosed. A substrate is provided. A plurality of pillars is disposed on the substrate. Each pillar has a plurality of epitaxial layers, has a first sidewall and a second sidewall. A trench is formed between the pillars. A common bottom electrode is disposed in a lower portion of the trench and surrounded by a node dielectric layer. A first insulating layer is disposed on the common bottom electrode inside the trench. A plurality of gate structures is disposed on the first sidewall and inside the trench. A second insulating layer is disposed inside the trench and adjacent to the gate structures. A third insulating layer, body line, and fourth insulating layer are respectively disposed on the substrate and located between the second insulating layer and the second sidewall.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.