PMOS three-terminal non-volatile memory element and method of programming
US7450431B1 · kind B1 · utility
3Cited by
13References
6Claims
0Family size
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Key dates
| Filing date | Aug 24, 2005 |
| Grant date | Nov 11, 2008 |
| Priority date | — |
| Expiry date | Sep 24, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C17/16
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A PMOS transistor is programmed as a non-volatile memory element by operating the PMOS transistor in accumulation mode. This facilitates merging the source and drain regions to form a low-resistance path because most heating occurs on the channel side of the gate dielectric, rather than on the gate terminal side. In a particular embodiment, boron is used as the dopant. Boron has a higher diffusivity than arsenic or phosphorous, which are typical n-type dopants. Boron's higher diffusivity promotes merging the source and drain regions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.