Determining reachable pins of a network of a programmable logic device
US7451420B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 11, 2006 |
| Grant date | Nov 11, 2008 |
| Priority date | — |
| Expiry date | May 15, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/398
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processor-implemented method is provided for determining reachable pins functionally connected to a network of a netlist that describes a programmable logic device (PLD) design. A netlist and an identification of the network in the netlist are input. Characterization data is input for one or more repeater modules that specify a first set of functionally connected pins of the repeater module. A second set is initialized with the pins of the network. For each pin in the second set that is one of the functionally connected pins of a first set, an additional pin may be added to the second set for each of the pins of a network for each of the functionally connected pins. The adding is repeated for each additional pin added to the second set. A specification of the pins from the second set is output as the reachable pins.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.