Determining controlling pins for a tile module of a programmable logic device
US7451425B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 11, 2006 |
| Grant date | Nov 11, 2008 |
| Priority date | — |
| Expiry date | Jan 9, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/34
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processor-implemented method is provided for determining controlling pins of a programmable logic device (PLD) design. A netlist that describes the PLD design and an identification of a tile module are input. Characterization data is input for a sub-module of the tile module that specifies a select input pin controlling a programmable function of the sub-module, which is either a multiplexer or a logic site. Characterization data is input for a configuration memory cell of the tile module that specifies a data output pin of the configuration memory cell. The controlling pin is determined for each select input pin of each instance of the sub-module of the tile module. The controlling pin of a select input pin is the data output pin of an instance of a configuration memory cell of the tile module. A specification is output of the select input pin and corresponding controlling pin.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.