Gate-induced strain for MOS performance improvement
US7452764B2 · kind B2 · utility
4Cited by
13References
6Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 1, 2005 |
| Grant date | Nov 18, 2008 |
| Priority date | — |
| Expiry date | Mar 1, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/0167
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method including forming a device on a substrate, the device including a gate electrode on a surface of the substrate; a first junction region and a second junction region in the substrate adjacent the gate electrode; and depositing a straining layer on the gate electrode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.