Methods for lateral current carrying capability improvement in semiconductor devices
US7453151B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 27, 2006 |
| Grant date | Nov 18, 2008 |
| Priority date | — |
| Expiry date | Dec 13, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/401
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor structure and methods for forming the same. The semiconductor structure includes (a) a substrate; (b) a first semiconductor device on the substrate; (c) N ILD (Inter-Level Dielectric) layers on the first semiconductor device, wherein N is an integer greater than one; and (d) an electrically conductive line electrically coupled to the first semiconductor device. The electrically conductive line is adapted to carry a lateral electric current in a lateral direction parallel to an interfacing surface between two consecutive ILD layers of the N ILD layers. The electrically conductive line is present in at least two ILD layers of the N ILD layers. The electrically conductive line does not comprise an electrically conductive via that is adapted to carry a vertical electric current in a vertical direction perpendicular to the interfacing surface.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.