Semiconductor chip having bond pads
US7453159B2 · kind B2 · utility
9Cited by
28References
24Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 27, 2006 |
| Grant date | Nov 18, 2008 |
| Priority date | — |
| Expiry date | Dec 27, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/30105
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor chip comprises a semiconductor substrate having integrated circuits formed on a cell region and a peripheral circuit region adjacent to each other. A bond pad-wiring pattern is formed on the semiconductor substrate. A pad-rearrangement pattern is electrically connected to the bond pad-wiring pattern. The pad-rearrangement pattern includes a bond pad disposed over at least a part of the cell region. Thus, with the embodiments of the present invention, the overall chip size can thereby be substantially reduced and an MCP can be fabricated without the problems mentioned above.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.