Efficient memory update process for on-the-fly instruction translation for well behaved applications executing on a weakly-ordered processor
US7454570B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 7, 2004 |
| Grant date | Nov 18, 2008 |
| Priority date | — |
| Expiry date | Sep 2, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3858
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A multiprocessor data processing system (MDPS) with a weakly-ordered architecture providing processing logic for substantially eliminating issuing sync instructions after every store instruction of a well-behaved application. Instructions of a well-behaved application are translated and executed by a weakly-ordered processor. The processing logic includes a lock address tracking utility (LATU), which provides an algorithm and a table of lock addresses, within which each lock address is stored when the lock is acquired by the weakly-ordered processor. When a store instruction is encountered in the instruction stream, the LATU compares the target address of the store instruction against the table of lock addresses. If the target address matches one of the lock addresses, indicating that the store instruction is the corresponding unlock instruction (or lock release instruction), a sync instruction is issued ahead of the store operation. The sync causes all values updated by the intermediate store operations to be flushed out to the point of coherency and be visible to all processors.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.