Computer processing system employing an instruction schedule cache

US7454597B2 · kind B2 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Krishnan K. Kailas · Tarrytown, US
• Ravi Nair · Briarcliff Manor, US
• Sumedh W. Sathaye · Austin, US
• Wolfram Sauer · Herrenberg, DE
• John-David Wellman · Hopewell Junction, US

Key dates

• Filing date: Jan 2, 2007
• Grant date: Nov 18, 2008
• Expiry date: May 16, 2027

Classification

• Technology area (CPC G): Physics
• CPC primary: G06F9/3858
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

A processor core and method of executing instructions, both of which utilizes schedules, are presented. Each of the schedules includes a sequence of instructions, an address of a first of the instructions in the schedule, an order vector of an original order of the instructions in the schedule, a rename map of registers for each register in the schedule, and a list of register names used in the schedule. The schedule exploits instruction-level parallelism in executing out-of-order instructions. The processor core includes a schedule cache that is configured to store schedules, a shared cache configured to store both I-side and D-side cache data, and an execution resource for requesting a schedule to be executed from the schedule cache. The processor core further includes a scheduler disposed between the schedule cache and the cache. The scheduler creating the schedule using branch execution history from a branch history table to create the instructions when the schedule requested by the execution resource is not found in the schedule cache. The processor core executes the instructions according to the schedule being executed. The method includes requesting a schedule from a schedul…