Method to reduce boron penetration in a SiGe bipolar device
US7456061B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 30, 2007 |
| Grant date | Nov 25, 2008 |
| Priority date | — |
| Expiry date | May 28, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/401
Abstract
The invention, in one aspect, provides a method of manufacturing a semiconductor device. This aspect includes forming gate electrodes in a non-bipolar transistor region of a semiconductor substrate, placing a polysilicon layer over the gate electrodes in the non-bipolar transistor region and over the semiconductor substrate within a bipolar transistor region. A protective layer is formed over the polysilicon layer. The protective layer has a weight percent of hydrogen that is less than about 9% and is selective to silicon germanium (SiGe), such that SiGe does not form on the protective layer. This aspect further includes forming emitters for bipolar transistors in the bipolar transistor region, including forming a SiGe layer under a portion of the polysilicon layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.