Forming ultra-shallow junctions
US7456068B2 · kind B2 · utility
51Cited by
12References
15Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 8, 2006 |
| Grant date | Nov 25, 2008 |
| Priority date | — |
| Expiry date | Oct 20, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/6211
Abstract
A method to form an ultra-shallow junction is described. In one embodiment, a replacement gate process is utilized to enable the overlap of a gate electrode over the regions of a semiconductor substrate where tip extensions reside. In another embodiment, a sacrificial spacer is utilized in conjunction with the replacement gate process. In one embodiment, an initial gate electrode is formed with a gate length smaller than the desired final gate length and is subsequently replaced with an expanded gate electrode having the desired gate length.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.