System and method for faceting via top corners to improve metal fill
US7456097B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 30, 2004 |
| Grant date | Nov 25, 2008 |
| Priority date | — |
| Expiry date | Oct 11, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76804
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A system and method is disclosed for providing an etch procedure to facet the top corners of a via in a semiconductor device. A vertical anisotropic dry etch process is applied through an aperture in a resist mask to etch through a dielectric layer down to a bottom conductor layer. The resist mask is removed and an etch process is applied to etch away corner portions of the dielectric layer. The etch process forms a flat sidewall surface in the portions of the dielectric layer that form the via. The flat sidewall surface is disposed at an obtuse angle with respect to the top surface of the dielectric layer and at an obtuse angle with respect to a vertical sidewall of the via cavity. The flat sidewall surface and the absence of sharp corners facilitate a subsequent metal fill process.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.