Building metal pillars in a chip for structure support
US7456098B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 13, 2006 |
| Grant date | Nov 25, 2008 |
| Priority date | — |
| Expiry date | Dec 13, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Stacked via pillars, such as metal via pillars, are provided at different and designated locations in IC chips to support the chip structure during processing and any related processing stresses such as thermal and mechanical stresses. These stacked via pillars connect and extend from a base substrate of the strip to a top oxide cap of the chip. The primary purpose of the stacked via pillars is to hold the chip structure together to accommodate any radial deformations and also to relieve any stress, thermal and/or mechanical, build-tip during processing or reliability testing. The stacked via pillars are generally not electrically connected to any active lines or vias, however in some embodiments the stacked via pillars can provide an additional function of providing an electrical connection in the chip.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.