Dynamic random access memory structure
US7456458B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Apr 13, 2006 |
| Grant date | Nov 25, 2008 |
| Priority date | — |
| Expiry date | Apr 22, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/20
Abstract
A dynamic random access memory structure having a vertical floating body cell includes a semiconductor substrate having a plurality of cylindrical pillars, an upper conductive region positioned on a top portion of the cylindrical pillar, a body positioned below the upper conductive portion in the cylindrical pillar, a bottom conductive portion positioned below the body in the cylindrical pillar, a gate oxide layer surrounding the sidewall of the cylindrical pillar and a gate structure surrounding the gate oxide layer. The upper conductive region serves as a drain electrode, the bottom conductive region serves as a source electrode and the body can store carriers such as holes. Preferably, the dynamic random access memory structure further comprises a conductive layer positioned on the surface of the semiconductor substrate to electrically connect the bottom conductive regions in the cylindrical pillars.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.