Split gate memory cell and method therefor
US7456465B2 · kind B2 · utility
13Cited by
13References
8Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 30, 2005 |
| Grant date | Nov 25, 2008 |
| Priority date | — |
| Expiry date | Oct 27, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/6893
- WIPO fieldMicro-structural and nano-technology
- WIPO sectorChemistry
Abstract
A split gate memory cell has a select gate, a control gate, and a charge storage structure. The select gate includes a first portion located over the control gate and a second portion not located over the control gate. In one example, the first portion of the select gate has a sidewall aligned with a sidewall of the control gate and aligned with a sidewall of the charge storage structure. In one example, the control gate has a p-type conductivity. In one example, the gate can be programmed by a hot carrier injection operation and can be erased by a tunneling operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.