Integrated circuit chip and integrated device
US7456505B2 · kind B2 · utility
18Cited by
4References
12Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 29, 2005 |
| Grant date | Nov 25, 2008 |
| Priority date | — |
| Expiry date | Dec 12, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3011
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Embodiments provide for integrated circuit chip and device having such an integrated circuit, in which different types of pads are arranged in separate rows. In one embodiment the pads are arranged to reduce the loop inductance of corresponding signal and power supply bond wires.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.