Patent · US Active

Clock and data recovery unit

US7457391B2 · kind B2 · utility

10Cited by

4References

31Claims

0Family size

Assignee

Infineon Technologies AG · DE

Inventors

Peter Gregorius · Munich, DE
Petyo Pentchev · Munich, DE

Key dates

Filing date	Mar 25, 2004
Grant date	Nov 25, 2008
Priority date	—
Expiry date	Aug 4, 2026

Classification

Technology area (CPC H)Electricity
CPC primaryH04L7/0083
WIPO fieldDigital communication
WIPO sectorElectrical engineering

Abstract

A clock and data recovery unit for recovering a received serial data bit stream having: phase adjustment means for adjustment of a sampling time in the center of a unit interval of the received data bit stream, wherein the phase adjustment means comprises means for generating equidistant reference phase signals, a phase interpolation unit, an oversampling unit, a serial-to-parallel-conversion unit, a binary phase detection unit, and a loop filter; and data recognition means for recovery of the received data stream which includes a number of parallel data recognition FIR-Filters, wherein each data recognition FIR-Filter comprises a weighting unit, a summing unit, and a comparator unit.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.