Patent · US Active

Method for generating fill and cheese structures

US7458053B2 · kind B2 · utility

8Cited by

10References

13Claims

0Family size

Assignee

Infineon Technologies AG · DE

Inventors

Erwin Ruderer · Borgo San Lazzaro, DE
Walther Lutz · Erding, DE
Bernhard Dobler · Erding, DE

Key dates

Filing date	Aug 16, 2006
Grant date	Nov 25, 2008
Priority date	—
Expiry date	Jun 7, 2027

Classification

Technology area (CPC G)Physics
CPC primaryG06F30/392
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A multi-pass method for designing at least a portion of a circuit layout on a substrate is provided which includes receiving or generating a first level frame including an electrical component; generating a fill pattern on the first level frame outside of a forbidden area of said first level frame; generating a next level frame, the next level frame including the first level frame and a next level fill area outside of the first level frame; and adding a conductor to the next level frame. The conductor is connected to the electrical component, a first portion of the conductor is in the first level frame and a second portion of the conductor is in the next level fill area. The method includes generating a next fill pattern on the next level fill area outside of a forbidden area of said next level fill area, modifying the first level forbidden area to extend at least over the electrical component and the first portion of the conductor, and removing any of the plurality of structures in the fill pattern that are within the modified first level forbidden area.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.