Yield-limiting design-rules-compliant pattern library generation and layout inspection
US7458060B2 · kind B2 · utility
1Cited by
3References
15Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 30, 2005 |
| Grant date | Nov 25, 2008 |
| Priority date | — |
| Expiry date | Aug 14, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/392
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and system are provided for analyzing process window compliance of an integrated circuit design. Aspects of the present invention include identifying layout pattern configurations that have process windows that fail to meet respective local performance specifications; searching for any layout pattern configurations in a design that substantially match any of the identified layout pattern configurations; and modifying any matching layout pattern configurations found in the design to make the layout pattern configurations compliant with their respective process windows.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.