Methods of forming self-aligned floating gates using multi-etching
US7459364B2 · kind B2 · utility
1Cited by
8References
14Claims
0Family size
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Key dates
| Filing date | Jul 11, 2005 |
| Grant date | Dec 2, 2008 |
| Priority date | — |
| Expiry date | Aug 2, 2026 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/978
Abstract
A method of forming a floating gate of a non-volatile memory device can include etching a mask pattern formed between field isolation regions in a field isolation pattern on a substrate to recess a surface of the mask pattern below an upper surface of adjacent field isolation regions to form an opening having a width defined by a side wall of the adjacent field isolation regions above the surface. Then the adjacent field isolation regions is etched to increase the width of the opening.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.