Ki-Su Na
5Patents
2h-index
10Co-inventors
40Inventor score
Filing activity: Apr 15, 2005 → Oct 29, 2009
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US7736963B2 | Method of forming a gate structure for a semiconductor device and method of forming a cell gate structure for a non-volatile memory device | Electricity | 3 | Active |
| US7902059B2 | Methods of forming void-free layers in openings of semiconductor substrates | Electricity | 3 | Active |
| US7459364B2 | Methods of forming self-aligned floating gates using multi-etching | Emerging Cross-Sectional Technologies | 1 | Active |
| US7629217B2 | Methods of forming void-free layers in openings of semiconductor substrates | Electricity | 0 | Active |
| US7160776B2 | Methods of forming a gate structure of a non-volatile memory device and apparatus for performing the same | Electricity | 0 | Expired |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.