Ultra thin body fully-depleted SOI MOSFETs
US7459752B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 23, 2006 |
| Grant date | Dec 2, 2008 |
| Priority date | — |
| Expiry date | Oct 28, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/017
Abstract
Ultra thin body fully-depleted silicon-on-insulator (SOI) metal-oxide-semiconductor field-effect-transistors (MOSFETs) in which the SOI thickness changes with gate-length variations thereby minimizing the threshold voltage variations that are typically caused by SOI thickness and gate-length variations are provided. Such a SOI MOSFET may include a SOI substrate having a SOI layer in which a first portion thereof has a thickness of less than 20 nm; a gate including a gate dielectric and a gate electrode located atop the first portion of the SOI layer having the thickness, the gate electrode having an upper surface and a bottom surface that have the same length or the bottom surface has a length that is greater than the upper surface; and source and drain diffusion regions located in a second portion of the SOI layer that is adjacent to the first portion, and the second portion of the SOI layer is thicker than the first portion.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.