Boosting for non-volatile storage using channel isolation switching
US7460404B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | May 7, 2007 |
| Grant date | Dec 2, 2008 |
| Priority date | — |
| Expiry date | May 7, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/0483
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Program disturb is reduced in non-volatile storage by preventing source side boosting in selected NAND strings. A self-boosting mode which includes an isolation word line is used. A channel area of an inhibited NAND string is boosted on a source side of the isolation word line before the channel is boosted on a drain side of the isolation word line. Further, storage elements near the isolation word line are kept in a conducting state during the source side boosting so that the source side channel is connected to the drain side channel. In this way, in selected NAND strings, source side boosting can not occur and thus program disturb due to source side boosting can be prevented. After the source side boosting, the source side channel is isolated from the drain side channel, and drain side boosting is performed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.