Scanner optimization for reduced across-chip performance variation through non-contact electrical metrology
US7460922B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 7, 2005 |
| Grant date | Dec 2, 2008 |
| Priority date | — |
| Expiry date | Feb 19, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG05B2219/37224
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
The disclosed embodiments reduce across-chip performance variation through non-contact electrical metrology. According to a feature is a process control system that includes a component that measures transistor electrical performance in a product wafer. Also included in the system is a mapping component that converts the transistor performance into exposure dose values and a process tool that communicates the exposure dose value to a scanner. The exposure dose value is fed back for optimization of future chip exposures. The disclosed embodiments directly optimize transistor performance, thus controlling an important parameter in many integrated circuits.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.