Floating point unit with fused multiply add and method for calculating a result with a floating point unit

US7461117B2 · kind B2 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Son Dao Trong · Stuttgart, DE
• Juergen Haess · Schenefeld, DE
• Christian Jacobi · West Park, US
• Klaus M. Kroener · Ehningen, DE
• Silvia M. Mueller · Altdorf, DE
• Jochen Preiss · Eppelheim, DE

Key dates

• Filing date: Feb 11, 2005
• Grant date: Dec 2, 2008
• Expiry date: Jun 1, 2027

Classification

• Technology area (CPC G): Physics
• CPC primary: G06F7/5443
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

The invention proposes a Floating Point Unit (1) with fused multiply add, with one addend operand (eb, fb) and two multiplicand operands (ea, fa; ec, fc), with a shift amount logic (2) which based on the exponents of the operands (ea, eb and ec) computes an alignment shift amount, with an alignment logic (3) which uses the alignment shift amount to align the fraction (fb) of the addend operand, with a multiply logic (4) which multiplies the fractions of the multiplicand operands (fa, fc), with a adder logic (5) which adds the outputs of the alignment logic (3) and the multiply logic (4), with a normalization logic (6) which normalizes the output of the adder logic (5), which is characterized in that a leading zero logic (7) is provided which computes the number of leading zeros of the fraction of the addend operand (fb), and that a compare logic (8) is provided which based on the number of leading zeros and the alignment shift amount computes select signals that indicate whether the most significant bits of the alignment logic (3) output have all the same value in order to: a) control the carry logic of the adder logic (5) and/or b) control a stage of the normalization logic (6).