Method and apparatus for suppressing duplicative prefetches for branch target cache lines
US7461237B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 20, 2005 |
| Grant date | Dec 2, 2008 |
| Priority date | — |
| Expiry date | Aug 30, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0862
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system that suppresses duplicative prefetches for branch target cache lines. During operation, the system fetches a first cache line into in a fetch buffer. The system then prefetches a second cache line, which immediately follows the first cache line, into the fetch buffer. If a control transfer instruction in the first cache line has a target instruction which is located in the second cache line, the system determines if the control transfer instruction is also located at the end of the first cache line so that a corresponding delay slot for the control transfer instruction is located at the beginning of the second cache line. If so, the system suppresses a subsequent prefetch for a target cache line containing the target instruction because the target instruction is located in the second cache line which has already been prefetched.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.