Methods for fabricating a stressed MOS device
US7462524B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 16, 2005 |
| Grant date | Dec 9, 2008 |
| Priority date | — |
| Expiry date | Sep 5, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/822
Abstract
Methods are provided for fabricating a stressed MOS device. One method comprises the steps of providing a substrate of a monocrystalline semiconductor material having a first lattice constant, and forming a conductive gate electrode overlying the substrate, the gate electrode having opposing sides and having a thickness. Sidewall spacers are formed on the opposing sides of the gate electrode and trenches are etched in the semiconductor substrate in alignment with the sidewall spacers. A portion of the thickness of the conductive gate electrode is also etched to leave a remaining portion of the conductive gate electrode. A stress inducing layer of material is grown on the remaining portion of the conductive gate electrode and filling the trenches, the stress inducing layer of material having a second lattice constant different than the first lattice constant.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.