Group III nitride compound semiconductor devices and method for fabricating the same
US7462867B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Sep 12, 2005 |
| Grant date | Dec 9, 2008 |
| Priority date | — |
| Expiry date | Sep 12, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10H20/8215
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A sapphire substrate 1 is etched so that each trench has a width of 10 μm and a depth of 10 μm were formed at 10 μm of intervals in a stripe pattern. Next, an AlN buffer layer 2 having a thickness of approximately 40 nm is formed mainly on the upper surface and the bottom surface of the trenches of the substrate 1. Then a GaN layer 3 is formed through vertical and lateral epitaxial growth. At this time, lateral epitaxial growth of the buffer layer 21, which was mainly formed on the upper surface of the trenches, filled the trenches and thus establishing a flat top surface. The portions of the GaN layer 3 formed above the top surfaces of the mesas having a depth of 10 μm exhibited significant suppression of threading dislocation in contrast to the portions formed above the bottoms of the trenches.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.