Dynamic deep depletion field effect transistor
US7462908B2 · kind B2 · utility
111Cited by
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8Claims
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Key dates
| Filing date | Jul 14, 2005 |
| Grant date | Dec 9, 2008 |
| Priority date | — |
| Expiry date | Aug 5, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/635
Abstract
A vertical conduction trench FET has a plurality of trenches containing conductive polysilicon gates. The mesas between the trenches have a source diffusion region connected to a common source electrode. The trenches are spaced so that the depletion regions induced by the trench gate will overlap to pinch off conduction through the mesa to turn off the device. The gate potential is pulsed. The polysilicon in the trenches may be separated into two insulated portions. The pulses may be applied simultaneously or sequentially to the polysilicon gates.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.