Operating method of non-volatile memory device
US7463530B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 30, 2006 |
| Grant date | Dec 9, 2008 |
| Priority date | — |
| Expiry date | Jun 29, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/685
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An operating method of non-volatile memory device is provided. The device includes memory cells having a semiconductor substrate, a stack layer, and source and drain regions disposed below a surface of the substrate and separated by a channel region. The stack layer includes an insulating layer disposed on the channel region, a charge storage layer disposed on the insulating layer, a multi-layer tunneling dielectric structure on the charge storage layer, and a gate disposed on the multi-layer tunneling dielectric structure. A negative bias is supplied to the gate to inject electrons into the charge storage layer through the multi-layer tunneling dielectric structure by −FN tunneling so that the threshold voltage of the device is increased. A positive bias is supplied to the gate to inject holes into the charge storage layer through the multi-layer tunneling dielectric structure by +FN tunneling so that the threshold voltage of the device is decreased.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.