Flash memory cell having reduced floating gate to floating gate coupling

US7465625B2 · kind B2 · utility

Inventors

• Been-Jon Woo · Saratoga, US
• Yudong Kim · Cupertino, US
• Albert Fazio · Los Gatos, US

Key dates

• Filing date: Oct 17, 2006
• Grant date: Dec 16, 2008
• Expiry date: Jan 25, 2027

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10B41/30

Abstract

According to an embodiment of the invention, a flash memory cell includes a first gate stack and a second gate stack having a film deposited across the gap between the first and second gate stacks so that the film creates a void between the first and second gate stacks. Dielectric materials may be used to reduce conductivity between the two stacks. A dielectric material that is resistant to conductivity has a low dielectric constant (k). The lowest-k dielectric material is air, which has a dielectric constant of approximately 1. By creating a void between the two gate stacks, the least conductive material (air) is left filling the space between the gate stacks, and the likelihood of parasitic coupling of two adjacent floating gates is substantially reduced.