Reducing latency in a channel adapter by accelerated I/O control block processing
US7466716B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 11, 2005 |
| Grant date | Dec 16, 2008 |
| Priority date | — |
| Expiry date | May 1, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L69/324
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
The present invention generally relates to digital network communication, and in particular to processing data according to the InfiniBand™ (IB) Protocol with reduced latency and chip costs in an InfiniBand™ type computer system. ID information in a packet header is obtained before the body of the packet has completely arrived at a receiving Channel adapter. The ID information is used to obtain work Queue Pair Context (QPC) and when needed an associated Work Queue Element (WQE), for operating on the data content of the packet being received.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.