Processor having content addressable memory for block-based queue structures
US7467256B2 · kind B2 · utility
11Cited by
62References
16Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 28, 2004 |
| Grant date | Dec 16, 2008 |
| Priority date | — |
| Expiry date | Dec 1, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L49/90
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
Queuing command information is stored in a content addressable memory (CAM) where a queuing command for a first queue is received, the CAM is examined to determine if commands for the first queue are present, and if commands for the first queue were found to be present, information is stored in a linked list for the received command in multiple CAM entries.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.